M.Tech in NS3 simulation

Build processes are too slow. Because most of the build time for Java projects is spent executing tests, researchers have focused on speeding up testing. They’ve integrated two complementary approaches into a system that seamlessly supports Ant and Maven JUnit build processes. The first approach, unit test virtualization, isolates in-memory dependencies among test cases, which otherwise are isolated inefficiently by restarting the Java Virtual Machine (JVM) before every test. The system supports just-in-time reinitialization of only the small portion of memory needed by the next test, reusing a single JVM.

The implementation of this approach is called VMVM (Virtual Machine in the Virtual Machine, pronounced “vroom vroom”). In addition, simple setup and tear-down resource management methods designed for sequential execution lead to conflicts when the resources are accessed concurrently. So, the second approach, virtualized unit test virtualization, isolates external dependencies such as files and network ports while long-running tests execute in parallel. For this, the system distributes testing jobs in round-robin manner among OS-level virtual machines. The result is, on average, a 51 percent speedup of application build times. The implementation of this approach is called VMVMVM (Virtual Machine in a Virtual Machine on a Virtual Machine “vroom vroom vroom”).

Connecting converters in cascade is a basic configuration of DC distributed power systems (DPS). The impedance interaction between individually designed converters may make the cascaded systembecome unstable. The previous presented stabilization approaches not only need to know the information of the regulated converter, but also have to know the characteristics of the other converters in the system, which are contradictory to the modularization characteristic of DC DPS. This letter proposes an adaptive-input-impedance-regulation (AIIR) method, which connects an adaptive virtual impedance in parallel with the input impedance of the load converter, to stabilize the cascaded system.

This virtual impedance can adaptively regulate its characteristic for different source converters. Therefore, with the AIIR method, all the load converters can be designed to a fixed standard module to stably adapt various source converters. In addition, at any cases, the AIIR approach only changes the load converter’s input impedance in a very small frequency range to keep the load converter’s original dynamic performance. The requirements on the AIIR method are derived and the control strategies to achieve the AIIR method is proposed. Finally, considering the worst stability problem that often occurs at the system whose source converter is an LC filter, a load converter cascaded with two different LC input filters is fabricated and tested to validate the effectiveness of the proposed AIIR control method.

The solution of polynomial equation systems is a problem frequently encountered by researchers in solving equations in specific derivatives, algebraic geometry and in optimization tasks. There exist various realizations of the Gröbner basis building method, but their serious disadvantage is the high complexity of calculations. Therefore, the algorithms currently employed for symbol-aided solutions are effective only for lower order polynomial equations systems.

The article offers a method based on tables individually corresponding to a polynomial which makes it possible to forgo the solution of the problem of dividing the matrix into parts in distributing the calculations on the systems enabling theparallel execution of the program. The tables corresponding to individual polynomials of the initialsystem or the basis can be distributed among the processors without decomposition.

With the coming of the era of big data, people are more concerned about data privacy. On the one hand, the users are more eager for fresh and low-latency search results than ever before. On the other hand, they do not want to open the search criteria. To this end, this paper proposes a scalable distributedprivate stream search system, in which the search criteria is hidden by homomorphic encryption technique with three buffers.

Most importantly, the system adopts shared-nothing architecture to support the horizontal scalability, and partitions the stream into segments to achieve parallel query and bitmap index-based storage. Experimental results show the effectiveness and efficiency of our method on private stream search.

Nowadays, it has become feasible to use mobile nodes as contributing entities in computing systems. In this paper, we consider a computational grid in which the mobile devices can share their idle resources to realize parallel processing. The overall computing task can be arbitrarily partitioned into multiple subtasks to be distributed to mobile resource providers (RPs). In this process, the computation load scheduling problem is highlighted.

Based on the optimization objective, i.e., minimizing the task makespan, a buyer-seller model in which the task sponsor can inspire the SPs to share their computing resources by paying certain profits, is proposed. The Stackelberg Pricing Game (SPG) is employed to obtain the optimal price and shared resource amount of each SP. Finally, we evaluate the performance of the proposed algorithm by system simulation and the results indicate that the SPG-based load scheduling algorithm can significantly improve the time gain in mobile grid systems.

Incremental path-based timing analysis (PBA) is a pivotal step in the timing optimization flow. A core building block analyzes the timing path-by-path subject to a critical amount of incremental changes on the design. However, this process in nature demands an extremely high computational complexity and has been a major bottleneck in accelerating timing closure. Therefore, we introduce in this paper a fast and scalable algorithm of incremental PBA with MapReduce ??? a recently popular programming paradigm in big-data era.

Inspired by the spirit of MapReduce, we formulate our problem into tasks that are associated with keys and values and perform massively-parallel map and reduce operations on adistributed system. Experimental results demonstrated that our approach can not only easily analyze huge deisgns in a few minutes, but also quickly revalidate the timing after the incremental changes. Our results are beneficial for speeding up the lengthy design cycle of timing closure.

The Smith-Waterman (SW) algorithm is universally used for a database search owing to its high sensitively. The widespread impact of the algorithm is reflected in over 8000 citations that the algorithm has received in the past decades. However, the algorithm is prohibitively high in terms of time and space complexity, and so poses significant computational challenges. Apache Spark is an increasingly popular fast big data analytics engine, which has been highly successful in implementing large-scale data-intensive applications on commercial hardware. This paper presents the first ever reported systemthat implements the SW algorithm on Apache Spark based distributed computing framework, with a couple of off-the-shelf workstations, which is named as SparkSW.

The scalability and load-balancing efficiency of the system are investigated by realistic ultra-large database from the state-of-the-art UniRef100. The experimental results indicate that 1) SparkSW is load-balancing for parallel adaptive on workloads and scales extremely well with the increases of computing resource, 2) SparkSW provides a fast and universal option high sensitively biological sequence alignments. The success of SparkSW also reveals that Apache Spark framework provides an efficient solution to facilitate coping with ever increasing sizes of biological sequence databases, especially generated by second-generation sequencing technologies.

This paper presents the results of a proof-of-concept implementation of a platform for distributed, real-time fault-tolerant control of parallel single-phase inverters, integrated in modular uninterruptible power supplies (UPS) or Battery Energy Storage Systems (BESS). Each inverter controller runs a basic clock which schedules all the real-time control tasks, according to the time-triggered paradigm. The clocks in the different inverters are kept in synchronism with each other, by applying a distributed clock synchronization algorithm.

The inverter controllers are connected through two serial buses. The first bus is a TDMA serial bus exclusively dedicated to the interchange of the short and frequent control variables needed to enforce load sharing between inverters. Each inverter applies to these variables a fault-tolerant variant of the averaging load sharing control method. The second bus is a CAN bus, with time stamping of messages, used to interchange the clock synchronization messages and the low bandwidth supervision and control variables.

High-fidelity nuclear power plant core simulations require solving the Boltzmann transport equation. In discrete ordinates methods, the most computationally demanding operation of this equation is the sweep operation. Considering the evolution of computer architectures, we propose in this paper, as a first step toward heterogeneous distributed architectures, a hybrid parallel implementation of the sweep operation on top of the generic task-based runtime system: PaRSEC. Such an implementation targets three nested levels of parallelism: message passing, multi-threading, and vectorization.

A theoretical performance model was designed to validate the approach and help the tuning of the multiple parameters involved in such an approach. The proposed parallel implementation of the Sweep achieves a sustained performance of 6.1 Tflop/s, corresponding to 33.9% of the peak performance of the targeted supercomputer. This implementation compares favourably with state-of-art solvers such as PartiSN, and it can therefore serve as a building block for a massively parallel version of the neutron transport solver DOMINO developed at EDF.

The market trend for next-generation communication systems has been toward miniaturization to meet the stunning ever increasing demand for wireless mobile data, leading to the need for distributed andparallel processing system configurations that are 10 times or more cost effective, flexible, high capacity, energy efficient, and scalable.

Reducing cost and size while increasing capacity and scalability requires several design paradigm shifts. This article presents design strategies to meet these goals.